Biography
I currently work full-time at Qualcomm Inc., Raleigh, NC.
I graduated in December 2012 with a Ph.D. from North Carolina State University. My advisor was Dr. Eric Rotenberg. Before joining NCSU, I studied at Temple Univeristy, Philadelphia, where I earned my Master's degree in Electrical Engineering. My advisor was Dr. Musoke Sendaula. For my Master's thesis, I had the opportunity to work with Dr. Amir Roth, at the University of Pennsylvania, Philadelphia. Prior to that, I completed my Bachelor of Engineering degree in Electronics Engineering from the University of Mumbai, India.
In my free time, I enjoy photography and playing the guitar.
Industry Experience
Senior Engineer, Qualcomm Inc., Raleigh, NC.
Jun 2013 - present.
+ Develop CPU performance models for next-generation of processors.
+ Perform experiments to analyze the performance impact of various micro-architectural optimizations.
+ Recommend novel architectural optimizations to improve performance of next-generation of processors.
Performance Tools Intern, Intel Corp., Santa Clara, CA.
Feb 2011 - Aug 2011.
+ Ported SEP, a performance-profiling tool used in Intel® VTune™, to enable performance monitoring on heterogeneous processor platforms.
+ Augmented the event-counting and event-sampling functionality of SEP to allow independent monitoring of different events on different processor types.
+ Analyzed SPEC CPU benchmarks using SEP to identify their performance characteristics on different types of processors.
+ Investigated parallelization of SPEC CPU benchmarks to improve performance and processor utilization on heterogeneous processor platforms.
PhD Research
Heterogeneous multi-core design, novel processor microarchitecture, instruction-level parallelism, microarchitecture simulation tools.
Dissertation
My research involves researching methods to recommend a set of core designs for a heterogeneous multi-core using the FabScalar framework. The constituent cores are chosen to maximize single-thread performance for a wide range of applications, but at the same time, minimize performance degradation due to application diversity and scheduling variability.
Other
I developed a cycle-accurate simulator for a customizable RTL model of a superscalar processor for the FabScalar framework. This tool can provide fast and accurate-to-RTL estimate of performance for studies such as design-space exploration of processors, pre-RTL evaluation of ideas, etc.
Publications
- A unified view of non-monotonic core selection and application steering in heterogeneous chip multiprocessors. S. Navada, N. K. Choudhary, S. V. Wadhavkar, and E. Rotenberg. Proceedings of the 22nd international conference on Parallel architectures and compilation techniques (PACT '13)pp.133-144, September 2013. [doi] [pdf]
- FabScalar: Automating Superscalar Core Design. N. K. Choudhary, S. V. Wadhavkar, T. A. Shah, H. Mayukh, J. Gandhi, B. H. Dwiel, S. Navada, H. H. Najaf-abadi, and E. Rotenberg. IEEE Micro, Special Issue: Micro's Top Picks from Computer Architecture Conferences, vol. 32, no. 3, pp.48-59, May-June 2012. [doi]
- FabScalar: Composing Synthesizable RTL Designs of Arbitrary Cores within a Canonical Superscalar Template. N. K. Choudhary, S. V. Wadhavkar, T. A. Shah, H. Mayukh, J. Gandhi, B. H. Dwiel, S. Navada, H. H. Najaf-abadi, and E. Rotenberg. Proceedings of the 38th IEEE/ACM International Symposium on Computer Architecture (ISCA-38), pp. 11-22, June 2011. [pdf]
- FabScalar. Niket K. Choudhary, Salil Wadhavkar, Tanmay Shah, Sandeep Navada, Hashem Hashemi, and Eric Rotenberg. Workshop on Architectural Research Prototyping (WARP), held in conjunction with ISCA-36, June 2009. [pdf]
Résumé
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Contact
Interests
Photography
Playing the guitar
Table-Tennis, Badminton
Learning French
Etceteras
WWW Computer Architecture Page
BASH Scripting Guide
GNU Emacs Reference Card
GDB Reference Card
Oral Presentation Advice by Mark Hill
PhD Comics