Brief Bio

I am a Ph.D. candidate at the ECE department at NC State University. My advisor is Dr. Eric Rotenberg.
Before joining NCSU, I studied at Temple Univeristy, Philadelphia, where I earned my Master's degree in Electrical Engineering. My advisor was Dr. Musoke Sendaula. For my Master's thesis, I had the opportunity to work with Dr. Amir Roth, at the University of Pennsylvania, Philadelphia. Prior to that, I completed my Bachelor of Engineering degree in Electronics Engineering from the University of Mumbai, India.

Research

Novel processor microarchitecture, heterogeneous multi-core design, instruction-level parallelism, microarchitecture simulation tools.

Present.
I am researching methods to recommend a set of core designs for a heterogeneous multi-core using the FabScalar framework. The constituent cores are chosen to maximize single-thread performance for a wide range of applications, but at the same time, minimize performance degradation due to application diversity and scheduling variability.

Past.
I developed a cycle-accurate simulator for a customizable RTL model of a superscalar processor for the FabScalar framework. This tool can provide fast and accurate-to-RTL estimate of performance for studies such as design-space exploration of processors, pre-RTL evaluation of ideas, etc.

Publications

  • FabScalar. Niket K. Choudhary, Salil Wadhavkar, Tanmay Shah, Sandeep Navada, Hashem Hashemi, and Eric Rotenberg. Workshop on Architectural Research Prototyping (WARP), held in conjunction with ISCA-36, June 2009. [pdf]
  • FabScalar: Composing Synthesizable RTL Designs of Arbitrary Cores within a Canonical Superscalar Template. N. K. Choudhary, S. V. Wadhavkar, T. A. Shah, H. Mayukh, J. Gandhi, B. H. Dwiel, S. Navada, H. H. Najaf-abadi, and E. Rotenberg. Proceedings of the 38th IEEE/ACM International Symposium on Computer Architecture (ISCA-38), pp. 11-22, June 2011. [pdf]
  • FabScalar: Composing Synthesizable RTL Designs of Arbitrary Cores within a Canonical Superscalar Template. N. K. Choudhary, S. V. Wadhavkar, T. A. Shah, H. Mayukh, J. Gandhi, B. H. Dwiel, S. Navada, H. H. Najaf-abadi, and E. Rotenberg. IEEE Micro Top Picks, Issue 3, May - June 2012. (To Appear) [pdf]

Industry Experience

Performance Tools Intern, Intel Corp., Santa Clara, CA.
Feb 2011 - Aug 2011.
- Ported SEP, a performance proling tool, to support heterogeneous processor platforms.
- Investigated techniques to improve resource utilization of SPEC benchmark suites on heterogeneous processor platforms.

Résumé

[txt] [pdf]

Coursework

CSC 505 : Design and Analysis of Algorithms [Spring 2009]
ECE 555 : Computer Control of Robots [Spring 2008]
ECE 721 : Advanced Microarchitecture [Fall 2007]
ECE 705 : Memory Systems Design [Fall 2007]
CSC 501 : Operating Systems Principles [Spring 2007]
ECE 561 : Embedded Systems Design [Spring 2007]
ECE 566 : Code Generation and Optimization [Spring 2007]
ECE 506 : Architecture of Parallel Computers [Fall 2006]
ECE 546 : VLSI Systems Design [Fall 2006]
ECE 791G: Special Topics - Multicore Architectures [Fall 2006]

Contact

Partners Building I, Suite 2300
Campus Box 7256
Raleigh NC 27695-7256
'salil_wadhavkar'-(at)-'ncsu'-dot-'edu'

Personal Interests

Photography
Playing the guitar
Table-Tennis, Badminton
Learning French
Reading random articles on Wikipedia

Etceteras

WWW Computer Architecture Page
BASH Scripting Guide
GNU Emacs Reference Card
GDB Reference Card
Oral Presentation Advice by Mark Hill
PhD Comics